Interview - VLSI Verilog Part 1

1) Design a RAM using Verilog.

Interview - VLSI Perl Part 1

1) What is a 'Package' in Perl?
'Package' declares the compilation unit as being in the given namespace. It provides a mechanism for alternative namespaces to protect packages from stomping on each other's variables.

Interview - VLSI Design Part 2

1) Explain why & how a MOSFET works.
MOSFET: metal-oxide-semiconductor field-effect transistor. The MOSFET is a four-terminal device. The voltage applied to the gate terminal determines if and how much current flows between the source and the drain ports. Then explain the resistive region, saturation region and velocity saturation.

2) Draw Vds-Ids curve for a MOSFET. Show the curves with (a) increasing Vgs (b) increasing transistor width (c) Channel Length Modulation.
In the resistive region, the transistor behaves like a voltage-controlled resistor, while in the saturation region, it acts as a voltage-controlled current source (when the channel length modulation effect is ignored).

3) Explain the various MOSFET capacitances
The MOSFET capacitances include overlap capacitance (lateral diffusion), gate-to-channel capacitance (varies in three different regions) and junction capacitance (bottom-plate and side-wall junction).

4) Draw a CMOS Inverter. Explain its static and dynamic behavior.
static behavior:

• Voltage Transfer Characteristic (VTC): narrow transient region, high gain during the switching transition.
  
• switching threshold: defined as the point where Vin = Vout. We can balance the relative driving strengths of the PMOS and NMOS transistors to obtain symmetrical characteristics and maximize the noise margins. It's relatively insensitivetive to variations in the device ratio.
  
• noise margin: channel length modulation can not be ignored. A high gain in the transition region is desirable for larger noise margin.
  

dynamic behavior: the propagation delay of the CMOS inverter is determined by the time it takes to charge and discharge the load capacitance through the PMOS and NMOS transistors, respectively.

• load capacitances: gate-to-drain capacitance, diffusion capacitance, wiring capacitance, fanout capacitance.
  
• propagation delay: sizing the inverter properly to obtain a symmetrical VTC and to equate the high-to-low and low-to-high propagation delays. To deduce the propagation delay: 1) Reduce load capacitances; 2) Increase the W/L ratio of the transistors, when the external load is dominant; 3) Increase VDD to trade off energy dissipation for performance; 4) The Smaller PMOS devices yield a faster design at the expense of symmetry and noise margin.
  

6) What is Noise Margin? Explain the procedure to determine Noise Margin.
Use a piece-wise linear approximation for the VTC. The transition region is approximated by a straight line, the gain of which equals the gain at the switching threshold.

7) Given the expression for CMOS switching power dissipation.

8) What is Body Effect?
The body effect describes the changes in the threshold voltage by the change in the substrate bias voltage between source and body.

9) Describe the various effects of scaling?

10) What is Latchup? Explain Latchup with cross section of a CMOS inverter. How do you avoid Latch Up?
Latchup is the inadvertent creation of a low-resistance path between VDD and GND, causing catastrophic meltdown. The cross-coupled transistors form a bistable silicon-controlled rectifier (SCR). Latchup will be triggered when transient currents flow through the substrate, which causes Vsub to rise.
Prevention:

• A layer of insulating oxide (trench) surrounds both the NMOS and PMOS transistors, which breaks the parasitic SCR structure between these transistors.
• Use a thin expitaxial layer of lightly doped silicon on top of a heavily doped substrate that offers a low substrate resistance (minimize Rsub and Rwell).
• Place substrate and well traps close to each transistor. nMOS should be clustered together near GND and pMOS should be clustered together near VDD.
  
• SOI devices are inherently latchup-resistant.
  

Interview - VLSI Design Part 1

Question: what is the difference between Mealy and Moore state machines?

The Moore state machine uses only only entry actions, i.e., output depends only on the previous state. It may has more states and synchronous outputs. The Mealy state machine uses only input actions, i.e., output depends on input and previous state. It may has fewer states and asynchronous outputs. The ouput timing behavior is different. The output of Moore machine has one cycle "delay", whereas the output of Mealy machine is immediately available.

Question: How to solve setup and hold violations in the design?

Setup Time is the amount of time the synchronous input must be stable before the active edge of the clock. Hold Time is the amount of time the synchronous input must be stable after the active edge of the clock.

During the initial iterations only setup violations are fixed whereas hold violations are fixed only after the actual physical place and route information is available. Setup and hold violations are mutually exclusive. Setup violations can be fixed by reducing the combo delay (minimizing the logic level). Hold violations are fixed by increasing the combo delay or by inserting buffers such that it does not cause the setup violations. Increasing or decreasing delays by upsizing or downsizing the cells ripples back into the design and the whole design is to be taken into consideration for carrying out the STA again.

Question: how can you reduce dynamic power?

• Reduce switching activity by designing good RTL.
• Clock gating [Reference] (De-activate the clocks for functions that are not required)
  
• Architectural improvements
• Reduce supply voltage
• Use multi Vdd

Question: What is cross talk?

Switching of the signal in one net can interfere neighboring net due to cross coupling capacitance. Cross talk may lead setup or hold violation.

Question: what are High-Vt and Low-Vt cells?

Interview - VLSI Physical Design Part 2

1) Delay between shortest path and longest path in the clock is called ____.
a. Global skew
b. Local skew
c. Useful skew
d. Slack

2) Cross talk can be avoided by __.
a. Shielding the nets.
b. Decreasing the spacing between the metal layers.
c. Using lower metal layers.
d. Using long nets.

3) Prerouting means routing of ___.
a. PG nets. (Note: Power/Ground nets)
b. Signal nets.
c. IO nets.
d. Clock nets.

4) What is the goal of CTS?
a. Minimum Skew
b. Minimum EM
c. Minimum IR Drop
d. Minimum Slack

5) To achieve better timing ___ cells are placed in the critical path.
a. LVT
b. HVT
c. RVT
d. SVT

6) Leakage power is inversely proportional to __.
a. Threshold Voltage
b. Load Capacitance
c. Supply Voltage
d. Frequency

7) In OCV timing check, for setup time, ___.
a. Max delay is used for launch path and Min delay for capture path.
b. Min delay is used for launch path and Max delay for capture path.
c. Both Max delay is used for launch and capture path.
d. Both Min delay is used for launch and capture path.

8) To avoid cross talk, the shielded net is usually connected to __.
a. VSS
b. VDD
c. Both VDD and VSS
d. Clock

9) If the data is faster than the clock in Reg to Reg path ___ violation may come.
a. Hold
b. Setup
c. Both
d. None

10) Timing sanity check means (with respect to physical design) ___.
a. Checking timing of routed design with net delays.
b. Checking timing of routed design without net delays.
c. Checking timing of placed design with net delays.
d. Checking timing of unplaced design without net delays.

11) Which of the following is having highest priority at final stage (post-routed) of the design ___ ?
a. Hold violation
b. Setup violation
c. Skew
d. None

12) Which of the following is best suited for CTS?
a) CLKBUF
b) BUF
c) INV
d) CLKINV

13) Difference between Clock buff/inverters and normal buff/inverters is __.
a. Clock buff/inverters are having equal rise and fall times with high drive strengths compare to normal buff/inverters
b. Normal buff/inverters are having equal rise and fall times with high drive strengths compare to Clock buff/inverters.
c. Clock buff/inverters are slower than normal buff/inverters
d. Clock buff/inverters are faster than normal buff/inverters

14) What is the effect of high drive strength buffer when added in long net ?
a. Delay on the net decreases
b. Capacitance on the net increases
c. Delay on the net increases
d. Resistance on the net increases.

15) Delay of a cell depends on which factors ?
a. Input transition and Output load
b. Output transition and input load
c. Input transition and Output transition
d. Input load and Output Load.

16) What is routing congestion in the design ?
a. Ratio of required routing tracks to available routing tracks
b. Ratio of available routing tracks to required routing tracks
c. Depends on the routing layers available
d. None of the above

[Answer: a for all questions; Questions are from vlsifaq.blogspot.com]

Interview - VLSI Physical Design Part 1

Question: why do you use alternative routing approach HVH (Horizontal-Vertical-Horizontal) and VHV (Vertical-Horizontal-Vertical) ?

It allows routability of the design and better usage of routing resources. For example, HVH means that Metal 1 is routed horizontally, Metal 2 routed vertically, and Metal 3 horizontally. An alternative routing approach (VHV) provides much better results with respect to area, performance, and power consumption trade-offs. It's due to the significantly better pin accessibility, which results in higher utilization. VHV leads to shorter wire lengths and a reduced number of signal vias, which in turn, improves performance and reliability while reducing power. In addition, VHV shows better distribution of power to cells, with better control of IR drop.

[REF] http://www.design-reuse.com/articles/6434/under-the-hood-of-library-ip-by-brani-buric-and-mike-colwell-virage-logic.html


Question: how to get AND, OR, NAND, NOR, XOR, XNOR gate using 2:1 MUX ?


Question: what is metastability ?

When there are setup and hold time violation in any flip-flop, it enters a state where its output is unpredictable, either '1' or '0'. When a flip-flop is in metastable state, its output oscillate between '1' and '0'. How long it takes to settle down depends on the technology of the flip-flop.

Cases in which metastability occurs?

• When the input signal is an asynchronous signal.
• When the clock skew/slew is too much (rise and fall time are more than the tolerable values)
• When interfacing two domains operating at two different frequencies or at the same frequency but with different phase.
• When the combinational delay is such that flip-flop data input changes in the critical window (setup + hold window)

MTBF is Mean Time Between Failure. It gives us information on how often a particular element will fail or in other words, it gives the average time interval between two successive failures.

The most common way to tolerate metastability is to add one or more successive synchronizing flip-flops to the synchronizer. This approach allows for an entire clock period for metastable events in the first synchronizing flip-flop to resolve themselves. It simply reduce the probability and increase the latency in the synchronous logic's observation of input change.

[REF] http://www.asic-world.com/tidbits/metastablity.html

Question: in a system with insufficient hold time, will slowing down the clock frequency help?

No. Making data path slower can help hold time but it may result in setup violation.

Question: in a system with insufficient setup time, will slowing down the clock frequency help?

Yes. Making data path faster can also help setup time but it may result in hold violation.

Question: why power stripes routed in the top metal layers?

The resistivity of top metal layers are less and hence less IR drop (voltage drop) is seen in power distribution network. If power stripes are routed in lower metal layers this will use a good amount of lower routing resources and therefore it can create routing congestion.

[The questions above are coming from vlsifaq.blogspot.com]