HTML:
Great HTML/CSS tutorial site: htmldog; w3school;
HTML Validation;
HTML Editors: Amaya; Komodo Edit;
CSS:
Validators:
HTML Validator Service; CSS Validator Service; Link Checker;
Courses:
UMD CMSC122 Introducation to Computer Programming via the Web
Tuesday, November 10, 2009
Thursday, November 5, 2009
Wednesday, October 28, 2009
Tuesday, September 29, 2009
Dynamic Programming
Dynamic Programming Practice Problems
CODE
1. Maximum Value Contiguous Subsequence
NOTE: This algorithm skip the special case that all values are negative in the array.
2. Longest Increasing Subsequence
3. Integer Knapsack Problem (multiple copies)
4. Integer 0/1 Knapsack Problem
See ~/Algorithm/Dynamic_Programming/dp/dp.cpp
CODE
1. Maximum Value Contiguous Subsequence
NOTE: This algorithm skip the special case that all values are negative in the array.
2. Longest Increasing Subsequence
3. Integer Knapsack Problem (multiple copies)
4. Integer 0/1 Knapsack Problem
See ~/Algorithm/Dynamic_Programming/dp/dp.cpp
Wednesday, August 26, 2009
Interview - VLSI Perl Part 1
1) What is a 'Package' in Perl?
'Package' declares the compilation unit as being in the given namespace. It provides a mechanism for alternative namespaces to protect packages from stomping on each other's variables.
'Package' declares the compilation unit as being in the given namespace. It provides a mechanism for alternative namespaces to protect packages from stomping on each other's variables.
Monday, August 24, 2009
Interview - VLSI Design Part 2
1) Explain why & how a MOSFET works.
MOSFET: metal-oxide-semiconductor field-effect transistor. The MOSFET is a four-terminal device. The voltage applied to the gate terminal determines if and how much current flows between the source and the drain ports. Then explain the resistive region, saturation region and velocity saturation.
2) Draw Vds-Ids curve for a MOSFET. Show the curves with (a) increasing Vgs (b) increasing transistor width (c) Channel Length Modulation.
In the resistive region, the transistor behaves like a voltage-controlled resistor, while in the saturation region, it acts as a voltage-controlled current source (when the channel length modulation effect is ignored).
3) Explain the various MOSFET capacitances
The MOSFET capacitances include overlap capacitance (lateral diffusion), gate-to-channel capacitance (varies in three different regions) and junction capacitance (bottom-plate and side-wall junction).
4) Draw a CMOS Inverter. Explain its static and dynamic behavior.
static behavior:
Use a piece-wise linear approximation for the VTC. The transition region is approximated by a straight line, the gain of which equals the gain at the switching threshold.
7) Given the expression for CMOS switching power dissipation.
8) What is Body Effect?
The body effect describes the changes in the threshold voltage by the change in the substrate bias voltage between source and body.
9) Describe the various effects of scaling?
10) What is Latchup? Explain Latchup with cross section of a CMOS inverter. How do you avoid Latch Up?
Latchup is the inadvertent creation of a low-resistance path between VDD and GND, causing catastrophic meltdown. The cross-coupled transistors form a bistable silicon-controlled rectifier (SCR). Latchup will be triggered when transient currents flow through the substrate, which causes Vsub to rise.
Prevention:
MOSFET: metal-oxide-semiconductor field-effect transistor. The MOSFET is a four-terminal device. The voltage applied to the gate terminal determines if and how much current flows between the source and the drain ports. Then explain the resistive region, saturation region and velocity saturation.
2) Draw Vds-Ids curve for a MOSFET. Show the curves with (a) increasing Vgs (b) increasing transistor width (c) Channel Length Modulation.
In the resistive region, the transistor behaves like a voltage-controlled resistor, while in the saturation region, it acts as a voltage-controlled current source (when the channel length modulation effect is ignored).
3) Explain the various MOSFET capacitances
The MOSFET capacitances include overlap capacitance (lateral diffusion), gate-to-channel capacitance (varies in three different regions) and junction capacitance (bottom-plate and side-wall junction).
4) Draw a CMOS Inverter. Explain its static and dynamic behavior.
static behavior:
- Voltage Transfer Characteristic (VTC): narrow transient region, high gain during the switching transition.
- switching threshold: defined as the point where Vin = Vout. We can balance the relative driving strengths of the PMOS and NMOS transistors to obtain symmetrical characteristics and maximize the noise margins. It's relatively insensitivetive to variations in the device ratio.
- noise margin: channel length modulation can not be ignored. A high gain in the transition region is desirable for larger noise margin.
- load capacitances: gate-to-drain capacitance, diffusion capacitance, wiring capacitance, fanout capacitance.
- propagation delay: sizing the inverter properly to obtain a symmetrical VTC and to equate the high-to-low and low-to-high propagation delays. To deduce the propagation delay: 1) Reduce load capacitances; 2) Increase the W/L ratio of the transistors, when the external load is dominant; 3) Increase VDD to trade off energy dissipation for performance; 4) The Smaller PMOS devices yield a faster design at the expense of symmetry and noise margin.
Use a piece-wise linear approximation for the VTC. The transition region is approximated by a straight line, the gain of which equals the gain at the switching threshold.
7) Given the expression for CMOS switching power dissipation.
8) What is Body Effect?
The body effect describes the changes in the threshold voltage by the change in the substrate bias voltage between source and body.
9) Describe the various effects of scaling?
10) What is Latchup? Explain Latchup with cross section of a CMOS inverter. How do you avoid Latch Up?
Latchup is the inadvertent creation of a low-resistance path between VDD and GND, causing catastrophic meltdown. The cross-coupled transistors form a bistable silicon-controlled rectifier (SCR). Latchup will be triggered when transient currents flow through the substrate, which causes Vsub to rise.
Prevention:- A layer of insulating oxide (trench) surrounds both the NMOS and PMOS transistors, which breaks the parasitic SCR structure between these transistors.
- Use a thin expitaxial layer of lightly doped silicon on top of a heavily doped substrate that offers a low substrate resistance (minimize Rsub and Rwell).
- Place substrate and well traps close to each transistor. nMOS should be clustered together near GND and pMOS should be clustered together near VDD.
- SOI devices are inherently latchup-resistant.
Interview - VLSI Design Part 1
Question: what is the difference between Mealy and Moore state machines?
The Moore state machine uses only only entry actions, i.e., output depends only on the previous state. It may has more states and synchronous outputs. The Mealy state machine uses only input actions, i.e., output depends on input and previous state. It may has fewer states and asynchronous outputs. The ouput timing behavior is different. The output of Moore machine has one cycle "delay", whereas the output of Mealy machine is immediately available.
Question: How to solve setup and hold violations in the design?
Setup Time is the amount of time the synchronous input must be stable before the active edge of the clock. Hold Time is the amount of time the synchronous input must be stable after the active edge of the clock.
During the initial iterations only setup violations are fixed whereas hold violations are fixed only after the actual physical place and route information is available. Setup and hold violations are mutually exclusive. Setup violations can be fixed by reducing the combo delay (minimizing the logic level). Hold violations are fixed by increasing the combo delay or by inserting buffers such that it does not cause the setup violations. Increasing or decreasing delays by upsizing or downsizing the cells ripples back into the design and the whole design is to be taken into consideration for carrying out the STA again.
Question: how can you reduce dynamic power?
Switching of the signal in one net can interfere neighboring net due to cross coupling capacitance. Cross talk may lead setup or hold violation.
Question: what are High-Vt and Low-Vt cells?
The Moore state machine uses only only entry actions, i.e., output depends only on the previous state. It may has more states and synchronous outputs. The Mealy state machine uses only input actions, i.e., output depends on input and previous state. It may has fewer states and asynchronous outputs. The ouput timing behavior is different. The output of Moore machine has one cycle "delay", whereas the output of Mealy machine is immediately available.
Question: How to solve setup and hold violations in the design?
Setup Time is the amount of time the synchronous input must be stable before the active edge of the clock. Hold Time is the amount of time the synchronous input must be stable after the active edge of the clock.
During the initial iterations only setup violations are fixed whereas hold violations are fixed only after the actual physical place and route information is available. Setup and hold violations are mutually exclusive. Setup violations can be fixed by reducing the combo delay (minimizing the logic level). Hold violations are fixed by increasing the combo delay or by inserting buffers such that it does not cause the setup violations. Increasing or decreasing delays by upsizing or downsizing the cells ripples back into the design and the whole design is to be taken into consideration for carrying out the STA again.
Question: how can you reduce dynamic power?
- Reduce switching activity by designing good RTL.
- Clock gating [Reference] (De-activate the clocks for functions that are not required)
- Architectural improvements
- Reduce supply voltage
- Use multi Vdd
Switching of the signal in one net can interfere neighboring net due to cross coupling capacitance. Cross talk may lead setup or hold violation.
Question: what are High-Vt and Low-Vt cells?
Friday, August 21, 2009
Interview - VLSI Physical Design Part 2
1) Delay between shortest path and longest path in the clock is called ____.
a. Global skew
b. Local skew
c. Useful skew
d. Slack
2) Cross talk can be avoided by __.
a. Shielding the nets.
b. Decreasing the spacing between the metal layers.
c. Using lower metal layers.
d. Using long nets.
3) Prerouting means routing of ___.
a. PG nets. (Note: Power/Ground nets)
b. Signal nets.
c. IO nets.
d. Clock nets.
4) What is the goal of CTS?
a. Minimum Skew
b. Minimum EM
c. Minimum IR Drop
d. Minimum Slack
5) To achieve better timing ___ cells are placed in the critical path.
a. LVT
b. HVT
c. RVT
d. SVT
6) Leakage power is inversely proportional to __.
a. Threshold Voltage
b. Load Capacitance
c. Supply Voltage
d. Frequency
7) In OCV timing check, for setup time, ___.
a. Max delay is used for launch path and Min delay for capture path.
b. Min delay is used for launch path and Max delay for capture path.
c. Both Max delay is used for launch and capture path.
d. Both Min delay is used for launch and capture path.
8) To avoid cross talk, the shielded net is usually connected to __.
a. VSS
b. VDD
c. Both VDD and VSS
d. Clock
9) If the data is faster than the clock in Reg to Reg path ___ violation may come.
a. Hold
b. Setup
c. Both
d. None
10) Timing sanity check means (with respect to physical design) ___.
a. Checking timing of routed design with net delays.
b. Checking timing of routed design without net delays.
c. Checking timing of placed design with net delays.
d. Checking timing of unplaced design without net delays.
11) Which of the following is having highest priority at final stage (post-routed) of the design ___ ?
a. Hold violation
b. Setup violation
c. Skew
d. None
12) Which of the following is best suited for CTS?
a) CLKBUF
b) BUF
c) INV
d) CLKINV
13) Difference between Clock buff/inverters and normal buff/inverters is __.
a. Clock buff/inverters are having equal rise and fall times with high drive strengths compare to normal buff/inverters
b. Normal buff/inverters are having equal rise and fall times with high drive strengths compare to Clock buff/inverters.
c. Clock buff/inverters are slower than normal buff/inverters
d. Clock buff/inverters are faster than normal buff/inverters
14) What is the effect of high drive strength buffer when added in long net ?
a. Delay on the net decreases
b. Capacitance on the net increases
c. Delay on the net increases
d. Resistance on the net increases.
15) Delay of a cell depends on which factors ?
a. Input transition and Output load
b. Output transition and input load
c. Input transition and Output transition
d. Input load and Output Load.
16) What is routing congestion in the design ?
a. Ratio of required routing tracks to available routing tracks
b. Ratio of available routing tracks to required routing tracks
c. Depends on the routing layers available
d. None of the above
[Answer: a for all questions; Questions are from vlsifaq.blogspot.com]
a. Global skew
b. Local skew
c. Useful skew
d. Slack
2) Cross talk can be avoided by __.
a. Shielding the nets.
b. Decreasing the spacing between the metal layers.
c. Using lower metal layers.
d. Using long nets.
3) Prerouting means routing of ___.
a. PG nets. (Note: Power/Ground nets)
b. Signal nets.
c. IO nets.
d. Clock nets.
4) What is the goal of CTS?
a. Minimum Skew
b. Minimum EM
c. Minimum IR Drop
d. Minimum Slack
5) To achieve better timing ___ cells are placed in the critical path.
a. LVT
b. HVT
c. RVT
d. SVT
6) Leakage power is inversely proportional to __.
a. Threshold Voltage
b. Load Capacitance
c. Supply Voltage
d. Frequency
7) In OCV timing check, for setup time, ___.
a. Max delay is used for launch path and Min delay for capture path.
b. Min delay is used for launch path and Max delay for capture path.
c. Both Max delay is used for launch and capture path.
d. Both Min delay is used for launch and capture path.
8) To avoid cross talk, the shielded net is usually connected to __.
a. VSS
b. VDD
c. Both VDD and VSS
d. Clock
9) If the data is faster than the clock in Reg to Reg path ___ violation may come.
a. Hold
b. Setup
c. Both
d. None
10) Timing sanity check means (with respect to physical design) ___.
a. Checking timing of routed design with net delays.
b. Checking timing of routed design without net delays.
c. Checking timing of placed design with net delays.
d. Checking timing of unplaced design without net delays.
11) Which of the following is having highest priority at final stage (post-routed) of the design ___ ?
a. Hold violation
b. Setup violation
c. Skew
d. None
12) Which of the following is best suited for CTS?
a) CLKBUF
b) BUF
c) INV
d) CLKINV
13) Difference between Clock buff/inverters and normal buff/inverters is __.
a. Clock buff/inverters are having equal rise and fall times with high drive strengths compare to normal buff/inverters
b. Normal buff/inverters are having equal rise and fall times with high drive strengths compare to Clock buff/inverters.
c. Clock buff/inverters are slower than normal buff/inverters
d. Clock buff/inverters are faster than normal buff/inverters
14) What is the effect of high drive strength buffer when added in long net ?
a. Delay on the net decreases
b. Capacitance on the net increases
c. Delay on the net increases
d. Resistance on the net increases.
15) Delay of a cell depends on which factors ?
a. Input transition and Output load
b. Output transition and input load
c. Input transition and Output transition
d. Input load and Output Load.
16) What is routing congestion in the design ?
a. Ratio of required routing tracks to available routing tracks
b. Ratio of available routing tracks to required routing tracks
c. Depends on the routing layers available
d. None of the above
[Answer: a for all questions; Questions are from vlsifaq.blogspot.com]
Interview - VLSI Physical Design Part 1
Question: why do you use alternative routing approach HVH (Horizontal-Vertical-Horizontal) and VHV (Vertical-Horizontal-Vertical) ?
It allows routability of the design and better usage of routing r
esources. For example, HVH means that Metal 1 is routed horizontally, Metal 2 routed vertically, and Metal 3 horizontally. An alternative routing approach (VHV) provides much better results with respect to area, performance, and power consumption trade-offs. It's due to the significantly better pin accessibility, which results in higher utilization. VHV leads to shorter wire lengths and a reduced number of signal vias, which in turn, improves performance and reliability while reducing power. In addition, VHV shows better distribution of power to cells, with better control of IR drop.
[REF] http://www.design-reuse.com/articles/6434/under-the-hood-of-library-ip-by-brani-buric-and-mike-colwell-virage-logic.html
Question: how to get AND, OR, NAND, NOR, XOR, XNOR gate using 2:1 MUX ?
Question: what is metastability ?
When there are setup and hold time violation in any flip-flop, it enters a state where its output is unpredictable, either '1' or '0'. When a flip-flop is in metastable state, its output oscillate between '1' and '0'. How long it takes to settle down depends on the technology of the flip-flop.
Cases in which metastability occurs?
The most common way to tolerate metastability is to add one or more successive synchronizing flip-flops to the synchronizer. This approach allows for an entire clock period for metastable events in the first synchronizing flip-flop to resolve themselves. It simply reduce the probability and increase the latency in the synchronous logic's observation of input change.
[REF] http://www.asic-world.com/tidbits/metastablity.html
Question: in a system with insufficient hold time, will slowing down the clock frequency help?
No. Making data path slower can help hold time but it may result in setup violation.
Question: in a system with insufficient setup time, will slowing down the clock frequency help?
Yes. Making data path faster can also help setup time but it may result in hold violation.
Question: why power stripes routed in the top metal layers?
The resistivity of top metal layers are less and hence less IR drop (voltage drop) is seen in power distribution network. If power stripes are routed in lower metal layers this will use a good amount of lower routing resources and therefore it can create routing congestion.
[The questions above are coming from vlsifaq.blogspot.com]
It allows routability of the design and better usage of routing r
esources. For example, HVH means that Metal 1 is routed horizontally, Metal 2 routed vertically, and Metal 3 horizontally. An alternative routing approach (VHV) provides much better results with respect to area, performance, and power consumption trade-offs. It's due to the significantly better pin accessibility, which results in higher utilization. VHV leads to shorter wire lengths and a reduced number of signal vias, which in turn, improves performance and reliability while reducing power. In addition, VHV shows better distribution of power to cells, with better control of IR drop.[REF] http://www.design-reuse.com/articles/6434/under-the-hood-of-library-ip-by-brani-buric-and-mike-colwell-virage-logic.html
Question: how to get AND, OR, NAND, NOR, XOR, XNOR gate using 2:1 MUX ?
Question: what is metastability ?
When there are setup and hold time violation in any flip-flop, it enters a state where its output is unpredictable, either '1' or '0'. When a flip-flop is in metastable state, its output oscillate between '1' and '0'. How long it takes to settle down depends on the technology of the flip-flop.
Cases in which metastability occurs?
- When the input signal is an asynchronous signal.
- When the clock skew/slew is too much (rise and fall time are more than the tolerable values)
- When interfacing two domains operating at two different frequencies or at the same frequency but with different phase.
- When the combinational delay is such that flip-flop data input changes in the critical window (setup + hold window)
The most common way to tolerate metastability is to add one or more successive synchronizing flip-flops to the synchronizer. This approach allows for an entire clock period for metastable events in the first synchronizing flip-flop to resolve themselves. It simply reduce the probability and increase the latency in the synchronous logic's observation of input change.
[REF] http://www.asic-world.com/tidbits/metastablity.html
Question: in a system with insufficient hold time, will slowing down the clock frequency help?
No. Making data path slower can help hold time but it may result in setup violation.
Question: in a system with insufficient setup time, will slowing down the clock frequency help?
Yes. Making data path faster can also help setup time but it may result in hold violation.
Question: why power stripes routed in the top metal layers?
The resistivity of top metal layers are less and hence less IR drop (voltage drop) is seen in power distribution network. If power stripes are routed in lower metal layers this will use a good amount of lower routing resources and therefore it can create routing congestion.
[The questions above are coming from vlsifaq.blogspot.com]
Sunday, March 29, 2009
VLSI CAD Open Source Software
VLSI CAD:
VLSI CAD Bookshelf 2
OpenAccess:
si2.org; openedatools; openAccess wiki; DFM Dictionary
OpenAccess 2.2 C++ API Documentation;
Logic Synthesis and Vefication:
MVSIS; ABC;
FPGA:
VPR
Placement:
Dragon; NTUplacer; Feng Shui;
Routing:
A Fairly Good Router; MaizeRouter; BoxRouter; Labyrinth;
Misc:
EasyGL
Applets:
Animation of VLSI CAD algorithms
SAT Solving:
MiniSAT ; Boolean Satisfiability Research Group at Princeton
Open Source Project:
gEDA; Open Circuit Design;
VLSI CAD Bookshelf 2
OpenAccess:
si2.org; openedatools; openAccess wiki; DFM Dictionary
OpenAccess 2.2 C++ API Documentation;
Logic Synthesis and Vefication:
MVSIS; ABC;
FPGA:
VPR
Placement:
Dragon; NTUplacer; Feng Shui;
Routing:
A Fairly Good Router; MaizeRouter; BoxRouter; Labyrinth;
Misc:
EasyGL
Applets:
Animation of VLSI CAD algorithms
SAT Solving:
MiniSAT ; Boolean Satisfiability Research Group at Princeton
Open Source Project:
gEDA; Open Circuit Design;
EDA Contest
ISPD: ISPD Contest ; ISPD 2006
IWLS: IWLS Programming Challenge
ICCAD: SIGDA's CADathlon ; CADathlon03
IWLS: IWLS Programming Challenge
ICCAD: SIGDA's CADathlon ; CADathlon03
Monday, March 23, 2009
Wednesday, March 18, 2009
HDL
Verilog - Wiki
Tutorial:
Verilog Tutorial from www.asic-world.com
Verilog Tutorial - electornics.com
Reference:
On-line Verilog-1995 Quick Reference Guide
Sutherland HDL
Academic Courses:
MIT 6.111 Introductory Digital Systems Laboratory
Berkeley EECS150 Components and Design Techniques for Digital Systems
Tips & Guides:
A Verilog Designer Guide - doulos
Verilog Tools:
Verilog Tools - asic-world
Icarus Verilog: Icarus Verilog; The Icarus Verilog Wiki
Tutorial:
Verilog Tutorial from www.asic-world.com
Verilog Tutorial - electornics.com
Reference:
On-line Verilog-1995 Quick Reference Guide
Sutherland HDL
Academic Courses:
MIT 6.111 Introductory Digital Systems Laboratory
Berkeley EECS150 Components and Design Techniques for Digital Systems
Tips & Guides:
A Verilog Designer Guide - doulos
Verilog Tools:
Verilog Tools - asic-world
Icarus Verilog: Icarus Verilog; The Icarus Verilog Wiki
Tuesday, March 17, 2009
Wednesday, March 4, 2009
Tuesday, March 3, 2009
Saturday, February 28, 2009
C++ -- Standard Template Library
Vector:
1. In addition to operator [], vector defines the member function at() that checks the index. If the index is invalid, it will throw an object of class std::out_of_range. Code: 09Feb/feb28_1.cpp.
2. The assign() function will reinitialize vector. e.g., vec.assign(v0.begin(), v0.end()) or vec.assign(5,"Me")
Allocators:
1. In addition to operator [], vector defines the member function at() that checks the index. If the index is invalid, it will throw an object of class std::out_of_range. Code: 09Feb/feb28_1.cpp.
2. The assign() function will reinitialize vector. e.g., vec.assign(v0.begin(), v0.end()) or vec.assign(5,"Me")
Allocators:
Memory Management
Memory Management:
The Memory Management Reference
Memory management in various languages at The Memory Management Reference
Garbage Collection:
Garbage collection - Wiki
C++ Memory Management Innovation: GC allocator - from codeproject
A Garbage collector for C and C++
Garbage Collection in C++ - from Stackflow
Garbage Collection in C programs - Linux Journal
Automatic Garbage Collection in Java and C++
A Simple Garbage Collector for C++
C++ Standard Library Allocator:
C++ Standard Allocator, An Introduction and Implementation
A C++ Standard Allocator for the Standard Template Library
The Standard Librarian: What Are Allocators Good For?
User-Defined Allocator - For Nicolai M.Josuttis
Articles:
Memory management archive collection from open directory projects
Freestore management on C++ FAQ Lite
Unix and C/C++ Runtime Memory Management For Programmers
Inside Memory Management
LinuxMM: a wiki for documenting how memory works and for coordination new memory management development projects.
The Memory Management Reference
Memory management in various languages at The Memory Management Reference
Garbage Collection:
Garbage collection - Wiki
C++ Memory Management Innovation: GC allocator - from codeproject
A Garbage collector for C and C++
Garbage Collection in C++ - from Stackflow
Garbage Collection in C programs - Linux Journal
Automatic Garbage Collection in Java and C++
A Simple Garbage Collector for C++
C++ Standard Library Allocator:
C++ Standard Allocator, An Introduction and Implementation
A C++ Standard Allocator for the Standard Template Library
The Standard Librarian: What Are Allocators Good For?
User-Defined Allocator - For Nicolai M.Josuttis
Articles:
Memory management archive collection from open directory projects
Freestore management on C++ FAQ Lite
Unix and C/C++ Runtime Memory Management For Programmers
Inside Memory Management
LinuxMM: a wiki for documenting how memory works and for coordination new memory management development projects.
Friday, February 27, 2009
C++ Memory Management
C++ Memory Management - From Fear to Triumph
1. Alternatives have automated memory management. Python has reference-counted model, and Java has sophisticated garbage collector.
2. Memory errors come in two basic types: the dangling reference and the memory leak.
3. The hidden memory allocation inside classes is a side effect, we need consider available alternatives.
[1] Allow the user to supply her own buffer (e.g., as a parameter to the constructor)
[2] Use a member object instead of a pointer to a dynamically allocated object.
[3] Strictly local objects that are used only for the duration of a method call should be declared as automatic variables.
[4] Use an allocator object to get the memory, and allow the user to specify his owner allocator.
4. Techniques for C++ Memory Management
5. Return value optimization.
SimpleString return_by_value() {
// Constructing the return value helps to eliminate the temporary objects associated with return-by-value
return SimpleString("ReturnValueOptimization");
}
From: http://www.linuxdevcenter.com/pub/a/linux/2003/05/08/cpp_mm-1.html?page=1
Difference between malloc/free and new/delete
[1] malloc() allocates a bunch of bytes while 'new' does the allocation as well as the responsibility of calling the constructor.
[2] malloc() returns 'NULL' on failure while 'new' throws an exception object of type 'std::bad_alloc'.
[3] 'free()' on 'NULL' pointers is not safe while 'delete' is.
1. Alternatives have automated memory management. Python has reference-counted model, and Java has sophisticated garbage collector.
2. Memory errors come in two basic types: the dangling reference and the memory leak.
3. The hidden memory allocation inside classes is a side effect, we need consider available alternatives.
[1] Allow the user to supply her own buffer (e.g., as a parameter to the constructor)
[2] Use a member object instead of a pointer to a dynamically allocated object.
[3] Strictly local objects that are used only for the duration of a method call should be declared as automatic variables.
[4] Use an allocator object to get the memory, and allow the user to specify his owner allocator.
4. Techniques for C++ Memory Management
5. Return value optimization.
SimpleString return_by_value() {
// Constructing the return value helps to eliminate the temporary objects associated with return-by-value
return SimpleString("ReturnValueOptimization");
}
From: http://www.linuxdevcenter.com/pub/a/linux/2003/05/08/cpp_mm-1.html?page=1
Difference between malloc/free and new/delete
[1] malloc() allocates a bunch of bytes while 'new' does the allocation as well as the responsibility of calling the constructor.
[2] malloc() returns 'NULL' on failure while 'new' throws an exception object of type 'std::bad_alloc'.
[3] 'free()' on 'NULL' pointers is not safe while 'delete' is.
GCC - Compiling a C++ program
C++ compilation options:
-Wall and -W: When compiling with g++, the options -Wall and -w include extra warnings specific to C++ (the warnings relate to member functions and virtual classes).
-fno-default-inline: disables the default inlining of member functions defined in the bodies of C++ classes. Select this option if you prefer to control inlining yourself, or want to set a breakpoint on member functions that would otherwise be inlined.
-Wold-style-cast: highlights any uses of C-style casts in C++ programs.
Templates:
[1] The executables created by g++ using the C++ standard library will be linked to the shared library 'libstdc++', which is supplied as part of the default GCC installation. There are several versions of this library -- if you distribute executables using the C++ standard library you need to ensure that the recipient has a compatible version of 'libstdc++', or link your program statically using the command-line option -static.
[2] The recommended way to use templates with g++ is to follow the inclusion compilation model, where template definitions are placed in header files. This is the method used by the C++ standard library supplied with GCC itself. If a template function is used several times in a program it will be stored in more than one objet file. The GNU Linker ensures that only one copy is placed in the final executable.
[3] Explicite template instantiation: template functions are no longer compiled at the point where they are used, as a result of the -fno-implicit-templates option.
Goto: http://www.network-theory.co.uk/docs/gccintro/gccintro_53.html
-Wall and -W: When compiling with g++, the options -Wall and -w include extra warnings specific to C++ (the warnings relate to member functions and virtual classes).
-fno-default-inline: disables the default inlining of member functions defined in the bodies of C++ classes. Select this option if you prefer to control inlining yourself, or want to set a breakpoint on member functions that would otherwise be inlined.
-Wold-style-cast: highlights any uses of C-style casts in C++ programs.
Templates:
[1] The executables created by g++ using the C++ standard library will be linked to the shared library 'libstdc++', which is supplied as part of the default GCC installation. There are several versions of this library -- if you distribute executables using the C++ standard library you need to ensure that the recipient has a compatible version of 'libstdc++', or link your program statically using the command-line option -static.
[2] The recommended way to use templates with g++ is to follow the inclusion compilation model, where template definitions are placed in header files. This is the method used by the C++ standard library supplied with GCC itself. If a template function is used several times in a program it will be stored in more than one objet file. The GNU Linker ensures that only one copy is placed in the final executable.
[3] Explicite template instantiation: template functions are no longer compiled at the point where they are used, as a result of the -fno-implicit-templates option.
Goto: http://www.network-theory.co.uk/docs/gccintro/gccintro_53.html
Monday, February 23, 2009
Thursday, February 19, 2009
Linux-C/C++
Learning C++ With Linux: an achive from Linux journal, suitable for newbie.
Linux C++ Software Development - from yolinux.com: links to Linux C++ GUI frameworks, APIs, IDEs, as well as C++ tips for Linux developers.
Linux C++ Software Development - from yolinux.com: links to Linux C++ GUI frameworks, APIs, IDEs, as well as C++ tips for Linux developers.
Design Pattern
Design patterns were originally grouped into the categories Creational patterns, Structural patterns, and Behavioral patterns, and described them using the concepts of delegation, aggregation, and consultation.
Wiki:
Design Pattern - wiki
Singleton pattern - wiki
General:
C++ Design Pattern: What is a Design Pattern (CodeGuru)
Design Patterns
Wiki:
Design Pattern - wiki
Singleton pattern - wiki
General:
C++ Design Pattern: What is a Design Pattern (CodeGuru)
Design Patterns
Tuesday, February 17, 2009
Programmer's Homepage
Export level:
Bjarne Stroustrup: C++'s father
John K. Ousterhout: invertor of Tcl language
Stan Lippman's Blog: autho of "C++ Primer"
Author level:
Steve McConnell's Homepage: author of "Code Complete"
Scott Meyers: author of Effective C++
Herb Sutter: author of Exceptional C++
Andrei Alexandrescu: author of "C++ Coding Standards" & "Modern C++ Design"
Nicolai M.Josuttis: author of "The C++ Standard Library"
Industry Guru level:
Joel on Software
John Graham-Cumming: create open source POPFile email filtering program
Maciej Sobczak: from Switzerland who are master on C++ and Tcl programming.
Brad Appleton's Home Page : a software development specialist.
David A. Wheel
Programmer's Corner@tmh: some c++ and perl resources
The Cantrip Corpus: in the ISO/ANSI C++ Standard committee
Pete Isensee: lots of C++ related papers and presentations
Kegel Homepage: lots of programming, IT suff
Industry Technical Level:
Shlomi Fish's Homepage
Academic:
Douglas C. Schmidt: CS professor, have some good material about C++/OOP
Cliff Green: a repository for programming teaching materials and technical articles
Techinical Blog:
Beans
Deepen C++ - blogspot
Yonat Sharon
C++ Soup
Bjarne Stroustrup: C++'s father
John K. Ousterhout: invertor of Tcl language
Stan Lippman's Blog: autho of "C++ Primer"
Author level:
Steve McConnell's Homepage: author of "Code Complete"
Scott Meyers: author of Effective C++
Herb Sutter: author of Exceptional C++
Andrei Alexandrescu: author of "C++ Coding Standards" & "Modern C++ Design"
Nicolai M.Josuttis: author of "The C++ Standard Library"
Industry Guru level:
Joel on Software
John Graham-Cumming: create open source POPFile email filtering program
Maciej Sobczak: from Switzerland who are master on C++ and Tcl programming.
Brad Appleton's Home Page : a software development specialist.
David A. Wheel
Programmer's Corner@tmh: some c++ and perl resources
The Cantrip Corpus: in the ISO/ANSI C++ Standard committee
Pete Isensee: lots of C++ related papers and presentations
Kegel Homepage: lots of programming, IT suff
Industry Technical Level:
Shlomi Fish's Homepage
Academic:
Douglas C. Schmidt: CS professor, have some good material about C++/OOP
Cliff Green: a repository for programming teaching materials and technical articles
Techinical Blog:
Beans
Deepen C++ - blogspot
Yonat Sharon
C++ Soup
VLSI CAD Courses Collection
VLSI Design Flow:
Design Flow - From U-Mass
VLSI Design Courses:
Project Based Material for Teaching VLSI Design and Fabrication
ASCI Design
Integrated System Design
Design of VLSI System
VLSI Design Principles
CS250 VLSI System Design - from UC Berkeley
General:
CAD for Digital Circuit Synthesis and Layout - from Prof. Jason Anderson@UT
ECE556 VLSI Physical and Logic Design Automation - from Sunysb
ECE565 VLSI Design Automation - from UIC
EECS 244 Introduction to Computer-Aided Design - from UCBerkeley
Physical
VLSI Physical Design Automation - from Prof. David Z. Pan@UTAustin
Introduction to VLSI CAD - from Northwest University
Logic:
Logic Synthesis and Verification EECS219B@UC Berkeley
Introduction to Logic Synthesis - from Adnan Aziz@UTAustin
ECE459 VLSI Algorithms - from Northwest
Advanced Methods in Logic Synthesis and Equivalence Checking - from Prof. Alan Mishchenko@Berkeley
Sequential Logic Synthesis and Verification - from Prof. Alan Mishchenko@Berkeley
Logic Synthesis for Hardware System - from Robert Brayton@Berkeley
VLSI Tools:
VLSI CAD Tools setup and tutorials
EDA Tools for Introductory VLSI Design Courses
Design Flow - From U-Mass
VLSI Design Courses:
Project Based Material for Teaching VLSI Design and Fabrication
ASCI Design
Integrated System Design
Design of VLSI System
VLSI Design Principles
CS250 VLSI System Design - from UC Berkeley
General:
CAD for Digital Circuit Synthesis and Layout - from Prof. Jason Anderson@UT
ECE556 VLSI Physical and Logic Design Automation - from Sunysb
ECE565 VLSI Design Automation - from UIC
EECS 244 Introduction to Computer-Aided Design - from UCBerkeley
Physical
VLSI Physical Design Automation - from Prof. David Z. Pan@UTAustin
Introduction to VLSI CAD - from Northwest University
Logic:
Logic Synthesis and Verification EECS219B@UC Berkeley
Introduction to Logic Synthesis - from Adnan Aziz@UTAustin
ECE459 VLSI Algorithms - from Northwest
Advanced Methods in Logic Synthesis and Equivalence Checking - from Prof. Alan Mishchenko@Berkeley
Sequential Logic Synthesis and Verification - from Prof. Alan Mishchenko@Berkeley
Logic Synthesis for Hardware System - from Robert Brayton@Berkeley
VLSI Tools:
VLSI CAD Tools setup and tutorials
EDA Tools for Introductory VLSI Design Courses
Wednesday, January 28, 2009
Vim Tips: Copy and paste text
Copy:
'Y' or 'yy': copies (yanks) one or more lines.
10Y: copies 10 lines.
yG: copies all lines to the end of the file.
yw: yank text from the current cursor position to the end of the word.
y$: yank text from the current cursor position to the end of the line.
Paste:
P(uppercase): to paste the text contained in the buffer above the current cursor position.
p(lowcase): to paste the text contained in the buffer below the current cursor position.
Insert:
I(uppercase) : insert to the start of the current line.
A(uppercase): append to the end of the current line.
r(lowcase) : overwrite one character. After overwriting the simple character, go back to command mode.
R(lowcase): enter insert mode but replace characters after than inserting.
Entering visual mode:
v(lowcase) : start hightlighting characters.
V(uppercase) : start hightlighting lines.
Moving:
0(zero) : to the beginnning of a line.
$ : to the end of a line.
Editing blocks of text:
(The Vim commands marked with (V) work in visual mode, when you've selected some text).
~ : change the case of characters.
>(V) : shift right.
<(V) : shift left.
y(V) : yank the highlighted text.
d(V) : delete the highlighted text.
'Y' or 'yy': copies (yanks) one or more lines.
10Y: copies 10 lines.
yG: copies all lines to the end of the file.
yw: yank text from the current cursor position to the end of the word.
y$: yank text from the current cursor position to the end of the line.
Paste:
P(uppercase): to paste the text contained in the buffer above the current cursor position.
p(lowcase): to paste the text contained in the buffer below the current cursor position.
Insert:
I(uppercase) : insert to the start of the current line.
A(uppercase): append to the end of the current line.
r(lowcase) : overwrite one character. After overwriting the simple character, go back to command mode.
R(lowcase): enter insert mode but replace characters after than inserting.
Entering visual mode:
v(lowcase) : start hightlighting characters.
V(uppercase) : start hightlighting lines.
Moving:
0(zero) : to the beginnning of a line.
$ : to the end of a line.
Editing blocks of text:
(The Vim commands marked with (V) work in visual mode, when you've selected some text).
~ : change the case of characters.
>(V) : shift right.
<(V) : shift left.
y(V) : yank the highlighted text.
d(V) : delete the highlighted text.
Tuesday, January 27, 2009
Perl Programming Topics
Perl Command-Line Options:
Perl Command-Line Options from perl.com
Overloading
Overloading from perl.com
Special Variables
Perl's Special Variables from perl.com
http://www.devdaily.com/perl/edu/articles/pl010010/
Development Practices
Ten Essential Development Practices
Perl Command-Line Options from perl.com
Overloading
Overloading from perl.com
Special Variables
Perl's Special Variables from perl.com
http://www.devdaily.com/perl/edu/articles/pl010010/
Development Practices
Ten Essential Development Practices
Vim tips: The basics of search and replace
Search:
1. /searchstring search forward through the file and ?searchstring search backwards through the file.
2. After running a search once, we can repeat it by using n in command mode, or N to reverse direction.
Replace:
syntax : [range] s/search/replace
1. The range is optional; if we just run :s/search/replace, it will search only the current line and match only the first occurrence of a term. We can add a range like:
:8, 10 s/search/replace/g
Without adding g, the search will match only the first instance of a string in any given line.
2. If you want to search an entire file, you can use % to indicate that as the range. If you wish to be asked for confirmation before Vim makes a substitution, add the confirm (c) option to the end of the search and replace command. (i) option will ignore case for the search pattern. (g) option will replace all occurrences in the line. Without this, Vim replaces only the first occurrences in each file.
:%s/search/replace/gc
Where you land:
1. To land on the last character in the matched string, add /e to your search: /string/e
2. To specify a cursor offset by line: /string/+2 or /string/-2
3. To specify a cursor offset by the beginning of the string or the end of the string: /string/s+2 or /string/e-3
1. /searchstring search forward through the file and ?searchstring search backwards through the file.
2. After running a search once, we can repeat it by using n in command mode, or N to reverse direction.
Replace:
syntax : [range] s/search/replace
1. The range is optional; if we just run :s/search/replace, it will search only the current line and match only the first occurrence of a term. We can add a range like:
:8, 10 s/search/replace/g
Without adding g, the search will match only the first instance of a string in any given line.
2. If you want to search an entire file, you can use % to indicate that as the range. If you wish to be asked for confirmation before Vim makes a substitution, add the confirm (c) option to the end of the search and replace command. (i) option will ignore case for the search pattern. (g) option will replace all occurrences in the line. Without this, Vim replaces only the first occurrences in each file.
:%s/search/replace/gc
Where you land:
1. To land on the last character in the matched string, add /e to your search: /string/e
2. To specify a cursor offset by line: /string/+2 or /string/-2
3. To specify a cursor offset by the beginning of the string or the end of the string: /string/s+2 or /string/e-3
Wednesday, January 21, 2009
C/C++ Programming Topics
Function Pointers:
DDJ: Generalized Function Pointers
Reference:
C++ Referece from CodeGuru Forum FAQ
Environment variables:
Environment variables in C++ from InformIT
DDJ: Generalized Function Pointers
Reference:
C++ Referece from CodeGuru Forum FAQ
Environment variables:
Environment variables in C++ from InformIT
Programming Course
The Tools of Programming at UTAustin
The Practice of Programming: Book; Class(UTAustin); Class(Princeton)
CMPUT201 from UAlberta: some practical programming skills
The Practice of Programming: Book; Class(UTAustin); Class(Princeton)
CMPUT201 from UAlberta: some practical programming skills
Monday, January 12, 2009
Friday, January 9, 2009
Vi/Vim
Wiki: Vim Wiki Main Page
Vi/Vim Referece:
Vi/Vim Reference - 1
Legacy:Vim
Plugins:
BASH IDE Plugin
Perl IDE Plugin
C/C++ IDE Plugin
Vi/Vim Referece:
Vi/Vim Reference - 1
Legacy:Vim
Plugins:
BASH IDE Plugin
Perl IDE Plugin
C/C++ IDE Plugin
Wednesday, January 7, 2009
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