Interview - VLSI Physical Design Part 2

1) Delay between shortest path and longest path in the clock is called ____.
a. Global skew
b. Local skew
c. Useful skew
d. Slack

2) Cross talk can be avoided by __.
a. Shielding the nets.
b. Decreasing the spacing between the metal layers.
c. Using lower metal layers.
d. Using long nets.

3) Prerouting means routing of ___.
a. PG nets. (Note: Power/Ground nets)
b. Signal nets.
c. IO nets.
d. Clock nets.

4) What is the goal of CTS?
a. Minimum Skew
b. Minimum EM
c. Minimum IR Drop
d. Minimum Slack

5) To achieve better timing ___ cells are placed in the critical path.
a. LVT
b. HVT
c. RVT
d. SVT

6) Leakage power is inversely proportional to __.
a. Threshold Voltage
b. Load Capacitance
c. Supply Voltage
d. Frequency

7) In OCV timing check, for setup time, ___.
a. Max delay is used for launch path and Min delay for capture path.
b. Min delay is used for launch path and Max delay for capture path.
c. Both Max delay is used for launch and capture path.
d. Both Min delay is used for launch and capture path.

8) To avoid cross talk, the shielded net is usually connected to __.
a. VSS
b. VDD
c. Both VDD and VSS
d. Clock

9) If the data is faster than the clock in Reg to Reg path ___ violation may come.
a. Hold
b. Setup
c. Both
d. None

10) Timing sanity check means (with respect to physical design) ___.
a. Checking timing of routed design with net delays.
b. Checking timing of routed design without net delays.
c. Checking timing of placed design with net delays.
d. Checking timing of unplaced design without net delays.

11) Which of the following is having highest priority at final stage (post-routed) of the design ___ ?
a. Hold violation
b. Setup violation
c. Skew
d. None

12) Which of the following is best suited for CTS?
a) CLKBUF
b) BUF
c) INV
d) CLKINV

13) Difference between Clock buff/inverters and normal buff/inverters is __.
a. Clock buff/inverters are having equal rise and fall times with high drive strengths compare to normal buff/inverters
b. Normal buff/inverters are having equal rise and fall times with high drive strengths compare to Clock buff/inverters.
c. Clock buff/inverters are slower than normal buff/inverters
d. Clock buff/inverters are faster than normal buff/inverters

14) What is the effect of high drive strength buffer when added in long net ?
a. Delay on the net decreases
b. Capacitance on the net increases
c. Delay on the net increases
d. Resistance on the net increases.

15) Delay of a cell depends on which factors ?
a. Input transition and Output load
b. Output transition and input load
c. Input transition and Output transition
d. Input load and Output Load.

16) What is routing congestion in the design ?
a. Ratio of required routing tracks to available routing tracks
b. Ratio of available routing tracks to required routing tracks
c. Depends on the routing layers available
d. None of the above

[Answer: a for all questions; Questions are from vlsifaq.blogspot.com]