Interview - VLSI Physical Design Part 1

Question: why do you use alternative routing approach HVH (Horizontal-Vertical-Horizontal) and VHV (Vertical-Horizontal-Vertical) ?

It allows routability of the design and better usage of routing resources. For example, HVH means that Metal 1 is routed horizontally, Metal 2 routed vertically, and Metal 3 horizontally. An alternative routing approach (VHV) provides much better results with respect to area, performance, and power consumption trade-offs. It's due to the significantly better pin accessibility, which results in higher utilization. VHV leads to shorter wire lengths and a reduced number of signal vias, which in turn, improves performance and reliability while reducing power. In addition, VHV shows better distribution of power to cells, with better control of IR drop.

[REF] http://www.design-reuse.com/articles/6434/under-the-hood-of-library-ip-by-brani-buric-and-mike-colwell-virage-logic.html


Question: how to get AND, OR, NAND, NOR, XOR, XNOR gate using 2:1 MUX ?


Question: what is metastability ?

When there are setup and hold time violation in any flip-flop, it enters a state where its output is unpredictable, either '1' or '0'. When a flip-flop is in metastable state, its output oscillate between '1' and '0'. How long it takes to settle down depends on the technology of the flip-flop.

Cases in which metastability occurs?

• When the input signal is an asynchronous signal.
• When the clock skew/slew is too much (rise and fall time are more than the tolerable values)
• When interfacing two domains operating at two different frequencies or at the same frequency but with different phase.
• When the combinational delay is such that flip-flop data input changes in the critical window (setup + hold window)

MTBF is Mean Time Between Failure. It gives us information on how often a particular element will fail or in other words, it gives the average time interval between two successive failures.

The most common way to tolerate metastability is to add one or more successive synchronizing flip-flops to the synchronizer. This approach allows for an entire clock period for metastable events in the first synchronizing flip-flop to resolve themselves. It simply reduce the probability and increase the latency in the synchronous logic's observation of input change.

[REF] http://www.asic-world.com/tidbits/metastablity.html

Question: in a system with insufficient hold time, will slowing down the clock frequency help?

No. Making data path slower can help hold time but it may result in setup violation.

Question: in a system with insufficient setup time, will slowing down the clock frequency help?

Yes. Making data path faster can also help setup time but it may result in hold violation.

Question: why power stripes routed in the top metal layers?

The resistivity of top metal layers are less and hence less IR drop (voltage drop) is seen in power distribution network. If power stripes are routed in lower metal layers this will use a good amount of lower routing resources and therefore it can create routing congestion.

[The questions above are coming from vlsifaq.blogspot.com]