Interview - VLSI Design Part 2

1) Explain why & how a MOSFET works.
MOSFET: metal-oxide-semiconductor field-effect transistor. The MOSFET is a four-terminal device. The voltage applied to the gate terminal determines if and how much current flows between the source and the drain ports. Then explain the resistive region, saturation region and velocity saturation.

2) Draw Vds-Ids curve for a MOSFET. Show the curves with (a) increasing Vgs (b) increasing transistor width (c) Channel Length Modulation.
In the resistive region, the transistor behaves like a voltage-controlled resistor, while in the saturation region, it acts as a voltage-controlled current source (when the channel length modulation effect is ignored).

3) Explain the various MOSFET capacitances
The MOSFET capacitances include overlap capacitance (lateral diffusion), gate-to-channel capacitance (varies in three different regions) and junction capacitance (bottom-plate and side-wall junction).

4) Draw a CMOS Inverter. Explain its static and dynamic behavior.
static behavior:

• Voltage Transfer Characteristic (VTC): narrow transient region, high gain during the switching transition.
  
• switching threshold: defined as the point where Vin = Vout. We can balance the relative driving strengths of the PMOS and NMOS transistors to obtain symmetrical characteristics and maximize the noise margins. It's relatively insensitivetive to variations in the device ratio.
  
• noise margin: channel length modulation can not be ignored. A high gain in the transition region is desirable for larger noise margin.
  

dynamic behavior: the propagation delay of the CMOS inverter is determined by the time it takes to charge and discharge the load capacitance through the PMOS and NMOS transistors, respectively.

• load capacitances: gate-to-drain capacitance, diffusion capacitance, wiring capacitance, fanout capacitance.
  
• propagation delay: sizing the inverter properly to obtain a symmetrical VTC and to equate the high-to-low and low-to-high propagation delays. To deduce the propagation delay: 1) Reduce load capacitances; 2) Increase the W/L ratio of the transistors, when the external load is dominant; 3) Increase VDD to trade off energy dissipation for performance; 4) The Smaller PMOS devices yield a faster design at the expense of symmetry and noise margin.
  

6) What is Noise Margin? Explain the procedure to determine Noise Margin.
Use a piece-wise linear approximation for the VTC. The transition region is approximated by a straight line, the gain of which equals the gain at the switching threshold.

7) Given the expression for CMOS switching power dissipation.

8) What is Body Effect?
The body effect describes the changes in the threshold voltage by the change in the substrate bias voltage between source and body.

9) Describe the various effects of scaling?

10) What is Latchup? Explain Latchup with cross section of a CMOS inverter. How do you avoid Latch Up?
Latchup is the inadvertent creation of a low-resistance path between VDD and GND, causing catastrophic meltdown. The cross-coupled transistors form a bistable silicon-controlled rectifier (SCR). Latchup will be triggered when transient currents flow through the substrate, which causes Vsub to rise.
Prevention:

• A layer of insulating oxide (trench) surrounds both the NMOS and PMOS transistors, which breaks the parasitic SCR structure between these transistors.
• Use a thin expitaxial layer of lightly doped silicon on top of a heavily doped substrate that offers a low substrate resistance (minimize Rsub and Rwell).
• Place substrate and well traps close to each transistor. nMOS should be clustered together near GND and pMOS should be clustered together near VDD.
  
• SOI devices are inherently latchup-resistant.